1. Field of the Invention
The present invention relates to current driving technique, and more particularly, to a current driver and a driving method capable of quickly generating driving current to drive a current driven device.
2. Description of the Prior Art
A current driver is utilized for generating a driving current to drive a current driven device, such as a laser diode, an LED, and other devices that are driven by current. In general, a current driver often utilizes a voltage buffer to control a gate voltage of a driving transistor, such that the driving transistor conducts and generates a driving current to drive a current driven device. In such a situation, when the current driver is switched from an off state to an activation state, the voltage buffer has to charge or discharge a gate of the driving transistor, to increase or decrease the gate voltage to be greater than or less than a source voltage by a threshold voltage, such that the driving transistor starts conducting and generating the driving current for enabling the driving current driven device to operate normally.
Please refer to FIG. 1A, which is a schematic diagram of a conventional current driver 10. The current driver 10 is utilized for generating a driving current Id to drive a current driven device 12. The current driver 10, for example, can include a voltage buffer 102, for receiving an input voltage Vin to generate an output voltage Vout, and further includes a bias current source 104, for receiving control of the output voltage Vout to generate the driving current Id1.
Specifically, the voltage buffer 102 includes an input terminal for receiving the input voltage Vin, another input terminal coupled to the bias current source 104, and an output terminal for providing the output voltage Vout. On the other hand, the bias current source 104 can, for example, include a driving switch Sd and one or more resistance elements, e.g. a resistor R. The driving switch Sd is disposed on a driving current path Pd, utilized for receiving the control of the output voltage Vout to conduct or cut off the driving current path Pd. The driving switch Sd can be realized by a driving transistor M1, e.g. an NMOSFET transistor, with a gate receiving the output voltage Vout of the voltage buffer 102, i.e. a gate voltage Vg1=the output voltage Vout, a drain coupled to the current driven device 12, and a source coupled to the resistor R and one of input terminals of the voltage buffer 102. The resistor R can be coupled between the source of the driving transistor M1 and a reference voltage level, e.g. a ground voltage level.
Please refer to FIG. 1B, which is a schematic diagram of waveforms of an activation signal Ena, the gate voltage Vg1 and the driving current Id of the current driver 10 shown in FIG. 1A, utilized for illustrating operating principles of the current driver 10. As shown in FIG. 1B, when the activation signal Ena is at a low voltage level, the voltage buffer 102 is not activated, causing the output voltage Vout, i.e. the gate voltage Vg1 of the driving transistor M1, to remain at a low voltage level. As a result, the driving transistor M1 cuts off and does not generate the driving current Id.
Conversely, after the activation signal Ena switches to a high voltage level to activate the voltage buffer 102, the output voltage Vout starts rising to charge the gate of the driving transistor M1. When the gate voltage Vg1 rises to be greater than the source voltage by a threshold voltage Vth1, the driving transistor M1 starts conducting and generating the driving current Id to drive the current driven device 12. Then, the voltage buffer 102 continues charging the gate of the driving transistor M1. Simultaneously, a negative feedback fixes the voltage Vr at a voltage level of the input voltage Vin maintaining a level of the driving current Id at Vin/R.
In such a situation, as shown in FIG. 1B, there exists a delay time Tdelay1 from the time when the level of the activation signal Ena is switched to the time when the driving transistor M1 starts conducting. In other words, the delay time Tdelay1 is a charging time required for increasing the gate voltage Vg1 by the threshold voltage Vth1. Additionally, some more time is required for the output voltage Vout of the voltage buffer 102 to rise. More disadvantageously, the driving transistor M1 is often realized by a power MOS with a greater size and hence a greater capacitance, the delay time Tdelay1 can actually be much longer. As a result, after the current driver 10 is activated, a lot of time is wasted before the current driven device 12 starts operating.
Similarly, operations of other conventional current drivers applying P-type driving transistors, which can be analogized by referring to the above operations, require a lot of discharging delay time as well. As a result, for applications that require repetitive switching on and off of the current driven device, high frequency operations can not be realized due to the excessively long delay time. Since the long delay time can not meet requirement of high frequency operations, there is a need for improvement of the prior art.